1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device such as a CMOS (complementary metal oxide semiconductor device) and an NMOS (N-type channel metal oxide semiconductor device). More particularly, the invention relates to a semiconductor integrated circuit which is useful as to a memory device.
2. Description of the Related Art
A MOS type integrated circuit device is fabricated in such a way that an element is separated by a field oxide film and that the source area and the drain area of the substrate are doped with impurities using the gate electrode as a mask by a self-alignment method.
However, one or two contacts have to be prepared for the source area and the drain area for one transistor device, which makes it difficult to realize a high density integrated circuit device due to the contact margin and the wiring space.
To cope with that problem, it has been proposed to use a semiconductor integrated circuit having a planar cell structure (Japanese Patent Applications Laying Open (KOKAI) Nos. 61-288464 and 63-96953).
In a planar cell structure, a continuous diffusion layer for source areas of a plurality of MOS transistors and a continuous diffusion layer for drain areas of the transistors are formed in parallel to each other in a substrate. On the substrate is formed a gate electrode which intersects the two diffusion layers through an insulation film.
In accordance with such a structure of the planar cell, it becomes unnecessary to form the field oxide film for separation of the element and besides the source areas and the drain areas of the common transistors can be used so that only one contact is required for several or tens of transistors, which makes it possible to realize a high density integrated circuit device.
However, in accordance with the planar cell structure, resistance of a diffusion layer is large since the layer is long, which lowers the function speed of the device since the bit line of the device is constituted from the diffusion layer.
When the memory cell is to be made more minute, a shallower junction is required. However, the planar cell structure does not allow using an LDD structure as the general transistors.
Also, if core ions are implanted into the device when the device is used as a mask ROM, the ions are also implanted to the long diffusion layer, which increases the junction capacitance and lowers the function speed of the device.